@Don_Adan, post #60
W 68060 rozpoznawanie wersji procesora za pomocą PCR to czysta przyjemność:
0430RRxx - pełna wersja 68060
0431RRxx - wersja EC lub LC
RR - bajt z rewizją procesora (np. 01 - rev. 1, 06 - rev. 6)
@*y, post #62
ESS—Enable Superscalar Dispatch
When this bit is set, the ability of the MC68060 to execute multiple instructions per
machine cycle is enabled. When this bit is cleared, the ability to execute multiple instructions per cycle is disabled and the MC68060 operates at a slower rate with lower performance. This bit is cleared at reset.
DFP—Disable Floating-Point Unit
When this bit is set, the on-chip FPU is disabled and any attempt to execute a floatingpoint instruction generates a line F emulator exception. When this bit is cleared, the FPU
executes all floating-point instructions. This bit is cleared at reset. Note that before this bit
is set via the MOVEC instruction, an FNOP must be executed to ensure that all floatingpoint exceptions are caught and handled. This would prevent unexpected floating-point
related exceptions to be reported when the FPU is re-enabled at a later time.
@mwb113, post #66
@UJP, post #67
@RomanWorkshop, post #68
@RomanWorkshop, post #70
@UJP, post #67
@mwb113, post #73
@*y, post #72
Bits 6–2—Reserved by Motorola for future use and must always be zero
@UJP, post #76