void GR_FV_Segment_To_Buffer(const int8 _buff_id, int32 x0, int32 y0, int32 x1, int32 y1) { int32 dx = x1 - x0; int32 dy = y0 - y1; int32 e2; if (x0 < x1) { int32 dx = x1 - x0; int err = dx + dy; for (;;) { GR_fv_buf_x[_buff_id][y0] = x0; GR_fv_buf_x_cell_id[_buff_id][y0] = GR_fv_proxy_cell_id; if (x0 == x1 && y0 == y1) break; e2 = err << 1; if (e2 >= dy) { err += dy; x0++; } if (e2 <= dx) { err += dx; y0++; } } } else { int32 dx = x0 - x1; int err = dx + dy; for (;;) { GR_fv_buf_x[_buff_id][y0] = x0; GR_fv_buf_x_cell_id[_buff_id][y0] = GR_fv_proxy_cell_id; if (x0 == x1 && y0 == y1) break; e2 = err << 1; if (e2 >= dy) { err += dy; x0--; } if (e2 <= dx) { err += dx; y0++; } } } }
@mateusz_s, post #1
GR_fv_buf_x[_buff_id][y0] = x0; GR_fv_buf_x_cell_id[_buff_id][y0] = GR_fv_proxy_cell_id;
if (x0 == x1 && y0 == y1) {PRZYPIS; break; } e2 = err << 1; if (e2 >= dy) { err += dy; x0++; } if (e2 <= dx) { err += dx; PRZYPIS; y0++; }
if(x1 < x0) {SWAP(x0, x1);} dx = x1 - x0;
@mateusz_s, post #1
void GR_FV_Segment_To_Buffer(const int8 _buff_id, int32 x0, int32 y0, int32 x1, int32 y1) { int32 dx = abs(x1-x0), sx = x0<x1 ? 1 : -1; int32 dy = abs(y1-y0), sy = y0<y1 ? 1 : -1; int32 err = (dx>dy ? dx : -dy)/2, e2; for(;;) { GR_fv_buf_x[_buff_id][y0] = x0; GR_fv_buf_x_cell_id[_buff_id][y0] = GR_fv_proxy_cell_id; if (x0==x1 && y0==y1) break; e2 = err; if (e2 >-dx) { err -= dy; x0 += sx; } if (e2 < dy) { err += dx; y0 += sy; } } }
@docent, post #4
@asman, post #7
@mateusz_s, post #5
.L7: move.l d1,d0 add.l d0,d0 cmp.l d0,d2 jbgt .L8 add.l d2,d1 addq.l #1,a1 .L8: cmp.l d0,a0 jblt .L4 add.l a0,d1 addq.l #1,d3 .L4: cmp.l a1,d4 jbne .L7 cmp.l d3,d5 jbne .L7 jbra .L11
.L7: move.l d1,d0 add.l d0,d0 cmp.l d0,d4 jbgt .L8 add.l d4,d1 addq.l #1,a1 .L8: cmp.l d0,d3 jblt .L4 add.l d3,d1 addq.l #1,d2 .L4: - move.l d5,a0 - lea (a0,d5.l*4),a0 - move.l a0,d0 - lsl.l #3,d0 - move.l d0,a4 - lea (a4,d2.l*4),a0 - move.l a1,(a0,a3.l) - move.l _GR_fv_proxy_cell_id,(a0,a2.l) cmp.l a1,d6 jbne .L7 cmp.l d2,d7 jbne .L7
void GR_FV_Segment_To_Buffer(const int8_t _buff_id, int32_t x0, int32_t y0, int32_t x1, int32_t y1) { int* GR_fv_buf_x_ptr; int* GR_fv_buf_x_cell_id_ptr; int32_t e2, err; int32_t dx = x1 - x0; int32_t dy = y0 - y1; GR_fv_buf_x_ptr = &GR_fv_buf_x[_buff_id][0]; GR_fv_buf_x_cell_id_ptr = &GR_fv_buf_x_cell_id[_buff_id][0]; if (x0 < x1) { dx = x1 - x0; err = dx + dy; for (;;) { GR_fv_buf_x_ptr[y0] = x0; GR_fv_buf_x_cell_id_ptr[y0] = GR_fv_proxy_cell_id; if (x0 == x1 && y0 == y1) break; e2 = err << 1; if (e2 >= dy) { err += dy; x0++; } if (e2 <= dx) { err += dx; y0++; } } } else { dx = x0 - x1; err = dx + dy; for (;;) { GR_fv_buf_x_ptr[y0] = x0; GR_fv_buf_x_cell_id_ptr[y0] = GR_fv_proxy_cell_id; if (x0 == x1 && y0 == y1) break; e2 = err << 1; if (e2 >= dy) { err += dy; x0--; } if (e2 <= dx) { err += dx; y0++; } } } }
.L7: move.l d1,d0 add.l d0,d0 cmp.l d0,d3 jbgt .L8 add.l d3,d1 addq.l #1,a0 .L8: cmp.l d0,d2 jblt .L4 add.l d2,d1 addq.l #4,a3 addq.l #4,a2 addq.l #1,a1 .L4: move.l a0,(a2) move.l _GR_fv_proxy_cell_id,(a3) cmp.l a0,d4 jbne .L7 cmp.l a1,d5 jbne .L7
@docent, post #9
move.l _GR_fv_proxy_cell_id,d6 ; zamiast d6 moze byc dowolny wolny rejestr Dx lub Ax .L7: move.l d1,d0 add.l d0,d0 cmp.l d0,d3 jbgt .L8 add.l d3,d1 addq.l #1,a0 .L8: cmp.l d0,d2 jblt .L4 add.l d2,d1 addq.l #4,a3 addq.l #4,a2 addq.l #1,a1 .L4: move.l a0,(a2) ; move.l _GR_fv_proxy_cell_id,(a3) move.l d6, (a3) cmp.l a0,d4 jbne .L7 cmp.l a1,d5 jbne .L7
@mateusz_s, post #1
@XoR, post #12
@mateusz_s, post #13
.L7: move.w d1,d0 lsl.w #1,d0 cmp.w d0,d4 jbgt .L8 add.w d4,d1 addq.w #1,a1 .L8: cmp.w d0,d3 jblt .L4 add.w d3,d1 addq.w #1,d2 .L4: move.w d2,a0 move.w a1,(a3,a0.l*2) move.w _GR_fv_proxy_cell_id,(a2,a0.l*2) cmp.w a1,d5 jbne .L7 cmp.w d2,d6 jbne .L7
@Don_Adan, post #11
.L7: move.w d1,d0 lsl.w #1,d0 cmp.w d0,d4 jbgt .L8 add.w d4,d1 addq.w #1,a1 .L8: cmp.w d0,d3 jblt .L4 add.w d3,d1 addq.w #1,d2 .L4: move.w d2,a0 move.w a1,(a3,a0.l*2) move.w d7,(a2,a0.l*2) cmp.w a1,d5 jbne .L7 cmp.w d2,d6 jbne .L7
@docent, post #15
@Kefir_Union, post #17
@docent, post #19
Poza tym, z tego co pamietam to skalowanie indeksu jest za darmo wiec nie byloby zadnego zysku.
move.l d2, a0
move.w a1,(a0)
add.l a2, a0
move.w d7,(a0)
@Kefir_Union, post #20
W takim przypadku obie instrukcje zapisu zajmą po 3 cykle
@docent, post #19
move.w d2,a0
move.w a1,(a3,a0.l*2)
move.w d7,(a2,a0.l*2)
@mateusz_s, post #1
void GR_FV_Segment_To_Buffer(const int8 _buff_id, int16 x0, int16 y0, const int16 x1, const int16 y1) { int16* fv_buf_x__READY = &GR_fv_buf_x[_buff_id][0]; int16* fv_buf_x_cell_id__READY = &GR_fv_buf_x_cell_id[_buff_id][0]; const int16 dy = y0 - y1; int16 e2; if (x0 < x1) { const int16 dx = x1 - x0; int16 err = dx + dy; for (;;) { e2 = err << 1; if (e2 >= dy) { err += dy; x0++; } if (e2 <= dx) { fv_buf_x__READY[y0] = x0; fv_buf_x_cell_id__READY[y0] = GR_fv_proxy_cell_id; err += dx; y0++; if (y0 == y1) { fv_buf_x__READY[y0] = x0; fv_buf_x_cell_id__READY[y0] = GR_fv_proxy_cell_id; break; } } } } else { const int16 dx = x0 - x1; int16 err = dx + dy; for (;;) { e2 = err << 1; if (e2 >= dy) { err += dy; x0--; } if (e2 <= dx) { fv_buf_x__READY[y0] = x0; fv_buf_x_cell_id__READY[y0] = GR_fv_proxy_cell_id; err += dx; y0++; if (y0 == y1) { fv_buf_x__READY[y0] = x0; fv_buf_x_cell_id__READY[y0] = GR_fv_proxy_cell_id; break; } } } } }
@Kefir_Union, post #20
1. Pozbywamy się mnożenia indeksu * 2 w tyvh liniach:Ja to zrozumialem jako propozycje optymalizacji, a to nic nie przyspieszy :)
move.w a1,(a3,a0.l*2)
move.w d7,(a2,a0.l*2)
...
i możemy zmienić na:
move.w a1,(a3,a0.l)
move.w d7,(a2,a0.l)
cykle: - - - - | - - - - | - - - - | - - - - | - - - - head tail cc move.w d2,a0 * * 2 0 2 move.w a1,(a3,a0.l*2) * * * * * * 4 0 6 move.w d7,(a2,a0.l*2) * * * * * * 4 0 6 bus: r w + + + + seq: exec1 + + calc2 dest + + + + exec2 + + calc3 dest + + + + exec3 + +
cykle: - - - - | - - - - | - - - - | - - - - | - - - - head tail cc move.l a3,a0 * * 2 0 2 add.w d2, a0 * * * * 4 0 4 move.w a1,(a0) * * * 0 1 3 add.l a2, a0 * * 2 0 2 move.w d7,(a0) * * * 0 1 3 bus r w + + + + seq: exec1 + + exec2 + + + + calc dest+exec3 + + exec4 + + calc dest+exec5 + +
@Kefir_Union, post #22