@Rafał A-3000, post #90
@glichtanski, post #91
@Rafał A-3000, post #92
@Rafał A-3000, post #92
@glichtanski, post #94
@Rafał A-3000, post #95
Być może kluczem tu jest sygnał z tych bramek.
@Rafał A-3000, post #95
A signal named /WAIT is provided for cache support. Asserting this signal will disable address
decoding of onboard Fast RAM by the RAMSEY chip and Zorro II/III bus accesses by the
BUSTER chip. Constraints imposed by the 68030 allow only 18ns to determine a cache hit. It is
often more feasible to assert /STERM before knowing whether the cycle is a cache hit and
rerunning the cycle via /HALT and /BERR if it is a miss. To achieve this functionality any
decoding of the first cycle by RAMSEY or BUSTER must be disabled by asserting /WAIT less
than 10ns after address valid. If the cycle is determined to miss a rerun is initiated and wait
deasserted for the secondary cycle. Assertion of /WAIT will keep /STERM, /CBACK, etc.
tristated by BUSTER or RAMSEY and may be controlled by the cache control logic.
@*y, post #99
@glichtanski, post #100
@glichtanski, post #105
@Rafał A-3000, post #110
@glichtanski, post #111
@Rafał A-3000, post #112
@glichtanski, post #111
@*y, post #116
Dysk RAD bez dodatkowych sterowników to dysk zakładany w pamięci CHIP. Ty chciałeś przebadać FAST!Zwiększyłem liczbę cylindrów do 1422 i z pamięci FAST zostało tylko około 500 kb wolej.
@*y, post #116
@Rafał A-3000, post #118