20.05.2020 20:43
[#1821]
Re: Nowe Turbo A1200/060 - WARP 1260
@marianoamigo, post #1819
In August 2018, the first prototype for A500 with MC68040 was built and also the second prototype with new FPGA (Artix-7), DDR3 RAM, and all integrated on single PCB. DDR3 memory was very problematic at the beginning. It is very demanding in terms of PCB design, signal integrity, etc. We've had a lot of moments of desperation before we finally get this working.
Another problem with DDR3 memory is that despite its bandwidth is high, but latency is huge. This huge latency is also the effect of the memory controller in FPGA. So why in the hell we've put DDR3 on this board? Because it is cheap and has nice bandwidth, and except CPU, there was also RTG graphics in mind.
For the graphics, DDR3 was perfect, and for CPU - well... modern CPU's have a lot of cache, so memory latency is not impacting them as much as old 68K's, which has only a few kB.
We decided to give this memory a chance and designed an L2 cache in between RAM and 68K CPU. It was a lot of work but made it possible to 68K run quite effective from this type of memory. It's not ideal though. In future updates, L2 cache will change to the so-called two-way, or maybe four-way cache solution and will also get some optimization.
Another problem with DDR3 memory is that despite its bandwidth is high, but latency is huge. This huge latency is also the effect of the memory controller in FPGA. So why in the hell we've put DDR3 on this board? Because it is cheap and has nice bandwidth, and except CPU, there was also RTG graphics in mind.
For the graphics, DDR3 was perfect, and for CPU - well... modern CPU's have a lot of cache, so memory latency is not impacting them as much as old 68K's, which has only a few kB.
We decided to give this memory a chance and designed an L2 cache in between RAM and 68K CPU. It was a lot of work but made it possible to 68K run quite effective from this type of memory. It's not ideal though. In future updates, L2 cache will change to the so-called two-way, or maybe four-way cache solution and will also get some optimization.
20.05.2020 20:58
[#1829]
Re: Nowe Turbo A1200/060 - WARP 1260
@Cizar, post #1825
DDR3 już też wypadają z obiegu, za rok zaczną wypadać DDR4 ;)
Najszybsze względem opóźnień vs zegar były chyba DDR 400MHz CL1.5
Można by było częściowo to rozwiązać dla DDR3, ale fpga musiałaby jednocześnie robić za swoisty cache L3 co by trochę bruździło, a komórek SRAMu to akurat znów bardzo dużo tam nie ma.
Najszybsze względem opóźnień vs zegar były chyba DDR 400MHz CL1.5
Można by było częściowo to rozwiązać dla DDR3, ale fpga musiałaby jednocześnie robić za swoisty cache L3 co by trochę bruździło, a komórek SRAMu to akurat znów bardzo dużo tam nie ma.
20.05.2020 21:12
[#1830]
Re: Nowe Turbo A1200/060 - WARP 1260
@abcdef, post #1829
a czy wiesz jak musi zapierda.... FPGA żeby to ogarnąć i ile taki kosztuje ? to nie jest ram prosty ram dynamiczny czy statyczny, zaprojektuj PCB do takich częstotliwości ( impedancja i długości ścieżek ) ... wypadaj ale ile były na rynku a CL1.5 nie wszystko mówi bo pierwszy dostęp jest o wiele dłuższy ... kolejna sprawa ze kontroler w FPGA nie jest sprzętowy jest to realizowane przez logikę a to dużo wolniejsze ....